Verilog: add test for conditional immediate assertion #577
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This adds a test for an immediate SystemVerilog assertion that is guarded by an if statement.
tautschnig
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Jun 25, 2024
Romy15200
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Aug 19, 2025
Verilog: add test for conditional immediate assertion
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This adds a test for an immediate SystemVerilog assertion that is guarded by an
ifstatement.